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19 November 2008
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Feature
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A/D, D/A Conversion for HDTV
With digital TV and flat-panel displays quickly
gaining momentum, A/D and D/A conversion of video and graphics signals in everyday consumer devices is becoming more widespread.
By Bart DeCanne
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When designing digital video systems, analog or mixed-signal issues are sometimes considered second nature, especially when the designer has a predominantly digital background. Because interfaces for video signals are - at least in the consumer domain - mostly analog, a
video system with digital processing will have at least one analog-to-digital (A/D) and/or digital-to-analog (D/A) conversion.
This article delves into different representations of video and graphics signals used in personal computers (PCs) and digital TVs (DTVs), including high-definition TV (HDTV) environments. In addition, important data converter parameters will be considered when selecting a device for an imaging application.
The analog interface between a component analog video source (for
example, a DVD player or set-top box) and an HDTV set will be presented as an example of practical use in digital video communication systems. Finally, the article will touch on some of the ongoing standardization work with respect to copy protection for the analog HDTV video interface.
Analog video signal representations
The most straightforward way to
represent video signals is by using gamma-corrected RGB values, denoted R'G'B'. Gamma correction corrects the nonlinear transfer characteristic of the display device. Historically, three video component signals were too expensive to record, process, or transmit. When color TV was introduced, a backward-compatible system was needed that would allow black and white receivers to receive only the luminance information. As a result, radical changes to the transmission format to include color could not be made, and
the color information had to be frequency interleaved within the luminance spectrum. This interleaving is the basis for all current TV systems: the National Television System Committee (NTSC) in the US and Japan, Phase Alternation Line (PAL) in most of Western Europe, and SECAM in France. One benefit of this interleaving was that when color TV was introduced, the channel bandwidth did not dramatically inC
R
ease and existing channel allocations could be preserved.
Composite vs. component video waveforms
Figure 1
shows the waveform of a color NTSC signal. (For the sake of clarity, we'll limit the discussion to 60-Hz-based systems. Equivalent standards exist for 50 Hz.) The signal levels are noted in IRE, and 140 IRE corresponds to 1V. The video/sync ratio of a color NTSC signal is 10:4 IRE. The voltage
difference between the blank and black levels in NTSC is 7.5 IRE. In the past, this difference was needed to completely shut off the retrace beam of the cathode ray tube (C
R
T) deflection. Today, it serves no purpose and most modern video systems (PC, HDTV) employ no setup.
The excursion of the 525/59.94 luma signal - from synctip to reference white - is nominally 1V. However, including the maximum chroma excursion of up to aprox. 131 IRE, the maximum amplitude of the NTSC signal is aprox.
1.2Vpp. The D/A conversion used for generating NTSC composite video, therefore, requires 1.2V output compliance.
From the R'G'B' color components, the gamma-corrected luminance Y' can be derived as a weighted sum of R'G'B' components, according to the ITU-BT.601 recommendation:
Y'601 = 0.299R' + 0.587G' + 0.114B'
C
B
respectively C
R
color difference signals are formed by scaling B'-Y' and R'-Y'. Y'C
B
C
R
signals are a natural format for the studio
transmission of video signals. For a standard-definition TV (SDTV) of 525 lines/59.94-Hz field rate, the sampling format is 13.5 MHz for Y and 6.75 MHz for both C
B
and C
R
. This format provides a total of 720 active pixels per line and a total data rate (including horizontal and vertical blanking) of 270 Mbit/sec (10-bit sampling resolution). This is the component digital 4:2:2 interface. (The ratio 4:2:2 refers to the sampling frequency of both color components being 1/2 of the
sampling frequency of Y.)
This 270-Mbps signal, known as the serial digital interface (SDI), is common in broadcast studio environments where it is serially routed between video equipment. A high definition variant of this uncompressed serial interface, at aprox. 1.5 Gbps, has been developed in recent years for HDTV production use. The Y'C
B
C
R
color space is a logical choice for modern broadcast, since MPEG-2 compression operates in this color space.
Component video systems,
standardized by the Society of Motion Picture and Television Engineers (SMPTE), employ no setup and have a 10:3 video/sync ratio.
Figure 2
shows the waveform of an analog HDTV signal. It has a horizontal sync with portions higher and lower than the blanking level, and is called a trilevel sync. Traditional SDTV component systems only have a negative sync of the same amplitude (300mV). Note that the blank (or black, since no setup occurs) to white maximum video
amplitude is 700mV. Because no color is superimposed, 700mV is also the maximum excursion required for a digital-to-analog converter (DAC) to generate SMPTE-compliant component video.
Some DACs targeted to video applications have separate blank and sync control inputs. When activated, the black input will provide an analog output level that corresponds to the blanking level, irrespective of the code input to the DAC. Activating the sync control input will insert a sync level. While the actual
full-scale output current can be slightly adjusted externally in most DACs, the relationship is fixed between maximum video and sync excursions. Most DACs will be compliant to older standards and have a 10:4 ratio with negative sync only.
The position of the blanking level between the R'G'B' and Y'P
B
'P
R
' representations of component video signals is significantly different (see
Figure 3
). Because P
B
' and P
R
' are
color differences, their amplitudes can be positive and negative with respect to blanking. However, for the Y' signal, blanking corresponds to the bottom level of the video signal range. Almost all commercially available video DACs have a 10:4 video/sync ratio and will position the blanking level correctly for the Y'R'G'B' signal type, but not for P
B
'P
R
'.
Data converter specs for video
There are several data converter specifications of specific importance in a video application. Other parameters, such as differential nonlinearity (DNL) and integral NL (INL), signal-to-noise ratio (SNR), or total harmonic distortion (THD) are generic for all converters and not included here. (See Resources for more information on these specifications.1)
Differential gain (DG), differential phase (DP). These
parameters are specifically related to the digitization of composite video. Differential gain is the percentage difference in the output amplitude of a small, high-frequency sine wave at two stated levels of a low-frequency signal on which it is superimposed. Differential phase is similar, but the change in output phase at two points is measured in degrees. Measurements of DG/DP indicate the amount of interaction that may occur between luminance and chrominance in composite video systems, where chrominance is
modulated using a 3.58-MHz (NTSC) or 4.43-MHz (PAL) subcarrier onto the luminance.
Output compliance voltage. Because video signals have defined standard voltage ranges, the high-speed current-steering DAC should be able to reach the full-scale output voltage by proper termination of the D/A output. For a video output connection, a 75-ý "double termination" is typically used, as shown in
Figure 4
. Therefore, the DAC
should reach 700mV full-scale (excluding sync) for component video and up to 1.2V for composite video, when its output sees a 37.5-ý termination.
Settling time. In some general-purpose applications (non-video), the settling time can be longer than the actual sampling period for a full-scale code transition. A common requirement in video is that the final analog output level be reached (within a typical 2% of its ideal value) before the next sample. This requirement
ensures that a single white pixel can be observed amidst a black background. Settling time is, therefore, seen as a speed-determining parameter for video DACs.
Glitch energy. Ideally, a DAC exhibits no undershoot/overshoot at large code transitions. Glitch energy refers to the undesired amount of energy (measured as voltage multiplied by time) present in the output waveform at such a transition. It can be intuitively understood as the area of the glitch seen on an oscilloscope,
at the time of such a code transition.
Video interfaces for PCs and workstations
Table 1
relates the VESA standards (common in PC environments) to some other video standards.
All formats, except the Video Electronics Standards Association (VESA) format, are intended for AC-coupled video inputs and use
the blank level as the signal reference. The VESA video-signal standard is intended for DC-coupled systems, and the reference level is the signal common.
The analog video output driver, display input, as well as all cabling are designed assuming a nominal impedance of 75V for the video transmission system.
For systems operating under the VESA standard, the following rules apply:
Video systems using the VESA video-signal standard shall not
supply or use synchronization pulses combined with luminance signals (no sync-on-green or equivalent). In this case, sync signals are always supplied to the display by means of separate, dedicated signal lines.
Horizontal sync pulses shall at all times continue to be supplied during the vertical sync pulse period. Under the VESA video-signal standard, use of a composite sync (on either separate sync line) is not permitted.
Synchronization signals will be communicated using one or more standard logic family levels. A strict definition of the expected signal levels for all cases is not given. However, the synchronization requirements for transistor-to-transistor logic (TTL) families can be seen in
Table 2
.
Besides generating an A/D sampling clock of the right frequency, the clock also needs to be positioned correctly when digitizing component video/graphics signals. Because
the analog signal is generated from a D/A output at the PC side, it needs to be sampled during the time window the D/A's output has settled to its output value. Depending on the D/A quality and the quality (that is, bandwidth) of the interconnection (for example, the length of monitor cable), this valid sampling window can only be a small fraction of the pixel period.
Since a Nyquist pattern of fs/2 horizontal frequency (alternating black/white vertical lines) is critical for correct phase
positioning, the phase-locked loop (PLL) must also provide an accurate phase-control method. Typically, silicon vendors provide a selection of 32 phases within a single pixel period on AFE ICs for FPD applications.
If the input signal needs to be digitized at full speed, the maximum ananlog-to-digital converter (ADC) speed needs to equl at least the pixel clock frequency of the highest video resolution supported.
Table 3
shows some popular PC graphics formats and
their resulting pixel clocks.
Video interfaces for digital TV
While for SDTV the video interface between the cable or satellite set-top box and TV set is NTSC (or S-video), the HDTV signal can only be transferred over a component video interface (CVI). A D/A is needed to convert the decompressed video signal from the MPEG-2 decoder (inside the set-top
box) to an analog CVI signal.
Eighteen Advanced Television Systems Committee (ATSC) defined formats have been created for DTV. This amalgam of formats was the only way to receive support from all involved parties: content providers, consumer electronics manufacturers (favoring the traditional interlaced structure currently in use for analog TV), and the PC industry (favoring progressive scan). Both the existing 4:3 and widescreen 16:9 aspect ratios are possible. Of these 18 modes, six are true HDTV
modes (1,080 x 1,920 and 720 & 1,280). The other formats provide for the transmission of conventional resolution TV in NTSC's 480 x 704 format or in a PC friendly VGA resolution of 640 x 480.
With respect to frame rates, 60I, 30P, and 24P are supported in all formats. The 24P frame rate is known as the film mode, since it corresponds with the 24 frames/s used in motion pictures. Using native 24P format to transmit film material avoids frame rate conversion at the encoder, resulting in more efficient
video compression. 1080I and 720P formats are in use today for HDTV in the US. (Note that a 60P mode for the highest picture resolution does not exist.)
The difference in the uncompressed data rate of both formats is over 2X. For an 8-vestigial sideband moduated (VSB) modulated DTV channel with a 19.4-Mbps capacity, more capacity is left for data services after video is compressed at the 720P format, than if the 1080I was used. Data services are more easily incorporated in the short term on general
CPU driven PCs than on dedicated TVs, and are seen by the PC industry as a possible additional form of revenue.
On the other hand, if the 720P format is used, clearly less HD remains, which is the consumer electronics sector's main argument against it.
Sampling rates
To arrive at the DAC speed needed to generate the decoded picture (for example, at
the set-top box output), let's look at the ATSC's highest-resolution formats. Note that these resolutions only show the active picture area of the screen. The total sC
R
een area formats are larger than the display formats of
Table 4
. The speed of the DAC is derived from the total sC
R
een size. Screen sizes for interlaced (1080I) and progressive (720P) HDTV are specified by SMPTE standards 274M and 296M, respectively. The formats are shown in
Figure 5
.
The resulting pixel rates, and hence, the required D/A converter speeds, are seen in
Table 6
.
Observe that for both formats, the pixel clock is equal, and that an 80-MHz DAC is fast enough to convert the decoded MPEG-2 signal back to the analog domain for an external interface with the HDTV display device, accepting component 1080I/720P input. It is interesting to note that the converter
sampling requirements for HDTV are actually less than the popular (SXGA) PC format (see
Table 3
).
The clock source for the DAC is normally the pixel clock, reconstructed by the MPEG-2 timestamp mechanism. However, in principle, the displayed image format in DTV is not required to be identical to the originally transmitted format. If it is not, however, an extra scaling step is needed downstream of the MPEG-2 decoder (with possibly a frame buffer) to
decouple the display pixel clock from the reconstructed original pixel clock.
Copy protection on the
analog CVI
Within the Consumer Electronics Association (CEA), a working group is currently drafting a standard for the implementation of copy protection on the analog CVI. Several other industry groups are working in the same area, but are more focused on
protection of digital content and digital interfaces.
Part of the analog CVI copy protection effort is to create a process for carrying data information over this interface that signals if its contents can be copied. The first implementation of this data service is the transmission of copy generation management system (CGMS) information on both SD and HD progressive type formats. Previously, copy protection existed only on composite interfaces.
Such an analog protection system (APS) implements analog
copy control on consumer devices (VC
R
s) or TV sets (premium channels) and can contain one or more of the following elements:
Pseudosync pulse or sync-suppression APS. By distorting the sync pulses, automatic gain circuits are invalidated.
Inverted color burst APS. Certain cycles of color-burst signals are inverted in phase.
Line shuffling APS. Video lines are shuffled according to a
certain pseudorandom sequence.
The CGMS data service is inserted on a dedicated line inside the vertical blanking interval, much like closed-captioning data in current NTSC. The data is amplitude-modulated and falls within the video range, so that the inclusion of this data poses no additional requirements on the DAC's output compliance voltage.
In the case of the CGMS data service, the payload includes 2 bits that indicate one of the following:
Copying
is permitted without restriction.
No more copies are allowed (a first-generation copy was made).
One generation of copies may be made.
No copying is permitted.
From an implementation point of view, an extra complexity comes up when converting between Y'P
B
'P
R
' and R'G'B' formats. The standard requires that equipment performing this conversion not affect the decodability of the
data carried in the CVI vertical blanking interval. Therefore, such color space conversion equipment will need to make special provision to transfer this data transparently.
Bart DeCanne
is a senior systems engineer in Texas Instrument's advanced analog products division in Dallas, TX. He holds an MSEE from the State University of Ghent, Belgium and can be contacted at
bdcanne@ti.com.
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